1. Field of the Invention
The present invention relates generally to computer systems and methods used in the design of electronic components, and more particularly to a system and method for the verification of an electronic component's design. Still more particularly, the present invention is a system and method for verification of local design rules applied to an integrated circuit layout.
2. Description of the Background Art
Computer systems and methods are used extensively in the design of integrated circuits. A key step in the integrated circuit design process is the verification of each element within a given integrated circuit's design or layout against one or more design rules. A design rule specifies a constraint that must be satisfied to ensure successful fabrication of the integrated circuit under consideration. Local design rules are those design rules that can be verified by analyzing design geometries located within a relatively small distance from each other. For example, a local design rule may require that the minimum spacing between adjacent metal edges be greater than a predetermined minimum distance, or an electrical "short" may occur.
As integrated circuit design complexity has increased, design rule verification has become more difficult and time-consuming. Currently, integrated circuit designs can contain millions of elements. In the prior art, most systems and methods for local design rule verification perform a set of design rule calculations for every element within the integrated circuit design. Verification of local design rules in such cases commonly requires millions of computations and several hours of computation time for even moderately complex integrated circuit designs. This in turn adversely affects the cost of integrated circuit design, making this prior art approach undesirable. Future integrated circuit manufacturing technologies will allow integrated circuit designs having ever-greater complexity, thereby exacerbating the problem.
An alternate approach to local design rule verification recognizes that in virtually all integrated circuit designs, any given element is typically repeated many times. Thus, the number of unique elements in an integrated circuit design is generally much smaller than the total number of elements in the design. The alternate approach attempts to perform the calculations necessary for local design rule verification only on the subset of unique elements, thereby greatly reducing the number of calculations required for the verification of an entire design.
The response of circuit designers to demands for increasing complexity has been an increasing use of circuit element duplication. For example, instead of laying out three separate transistors, it is more efficient to lay out a single-transistor "cell" and to reference the single-transistor cell three times via a higher-level cell. If the three transistors referenced in the higher level cell form a logic gate that is required ten times in the final circuit, an even higher-level cell could reference the three-transistor cell ten times. The original single-transistor cell would then occupy a third level in a design hierarchy. At this point, thirty transistors would appear in the fabricated integrated circuit, yet only one, namely, the single-transistor cell, was laid out.
Notwithstanding the multi-level nature of designs created in the above manner, the final integrated circuit as fabricated will be "flat," that is, all of its components will be placed in a plane when fabricated. While all of the interrelationships among design elements are defined in the hierarchical design, the interrelationships may not be apparent until they are considered in their two-dimensional form. For example, a single element placed in the "topmost" cell of the design hierarchy may have an obscure geometric relationship with many different elements of many lower-level cells. If even one of these relationships is missed during verification, the fabricated integrated circuit may not operate properly. Yet "flattening" each of the relationships according to their two-dimensional form severely multiplies the amount of work to be done and may make the amount of work too large to be handled by conventional computer systems.
The hierarchical nature of integrated circuit designs greatly adds to the complexity of local design rule verification via the alternate approach mentioned above. As a result, prior art systems and methods that have taken the alternate approach to local design rule verification have been unable to generate correct verification results in certain verification situations. More generally, prior art systems and methods have been unable to guarantee accurate local design rule verification results unless design constraints are imposed upon allowable hierarchical relationships between elements in an integrated circuit design. Typical examples of design constraints are as follows: 1) intrusion of a given cell's geometry into an area occupied by a related lower level cell, or "progeny" cell, may not occur more than two levels down in the design hierarchy; 2) two cells referenced by the same higher-level cell, or "sibling" cells, may not overlap; and 3) when polygons used to represent cells overlap, the use of polygons containing acute-angled vertices must be avoided to ensure correct verification results.
What is needed is a system and method for verification of local design rules that minimizes the number of computations required during verification while successfully analyzing integrated circuit designs regardless of the hierarchical relationships between their constituent elements.